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Freescale Semiconductor /MKL28Z7 /NVIC0 /NVIC0_ISER

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Interpret as NVIC0_ISER

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)SETENA0 0 (0)SETENA1 0 (0)SETENA2 0 (0)SETENA3 0 (0)SETENA4 0 (0)SETENA5 0 (0)SETENA6 0 (0)SETENA7 0 (0)SETENA8 0 (0)SETENA9 0 (0)SETENA10 0 (0)SETENA11 0 (0)SETENA12 0 (0)SETENA13 0 (0)SETENA14 0 (0)SETENA15 0 (0)SETENA16 0 (0)SETENA17 0 (0)SETENA18 0 (0)SETENA19 0 (0)SETENA20 0 (0)SETENA21 0 (0)SETENA22 0 (0)SETENA23 0 (0)SETENA24 0 (0)SETENA25 0 (0)SETENA26 0 (0)SETENA27 0 (0)SETENA28 0 (0)SETENA29 0 (0)SETENA30 0 (0)SETENA31

SETENA10=0, SETENA30=0, SETENA14=0, SETENA6=0, SETENA0=0, SETENA2=0, SETENA17=0, SETENA24=0, SETENA28=0, SETENA8=0, SETENA7=0, SETENA31=0, SETENA3=0, SETENA20=0, SETENA13=0, SETENA1=0, SETENA16=0, SETENA22=0, SETENA26=0, SETENA15=0, SETENA29=0, SETENA21=0, SETENA19=0, SETENA11=0, SETENA18=0, SETENA25=0, SETENA4=0, SETENA9=0, SETENA27=0, SETENA5=0, SETENA12=0, SETENA23=0

Description

Interrupt Set Enable Register

Fields

SETENA0

DMA0 channel 0/4 transfer complete interrupt set-enable bit

0 (0): write: no effect; read: DMA0 channel 0/4 transfer complete interrupt disabled

1 (1): write: enable DMA0 channel 0/4 transfer complete interrupt; read: DMA0 channel 0/4 transfer complete interrupt enabled
SETENA1

DMA0 channel 1/5 transfer complete interrupt set-enable bit

0 (0): write: no effect; read: DMA0 channel 1/5 transfer complete interrupt disabled

1 (1): write: enable DMA0 channel 1/5 transfer complete interrupt; read: DMA0 channel 1/5 transfer complete interrupt enabled
SETENA2

DMA0 channel 2/6 transfer complete interrupt set-enable bit

0 (0): write: no effect; read: DMA0 channel 2/6 transfer complete interrupt disabled

1 (1): write: enable DMA0 channel 2/6 transfer complete interrupt; read: DMA0 channel 2/6 transfer complete interrupt enabled
SETENA3

DMA0 channel 3/7 transfer complete interrupt set-enable bit

0 (0): write: no effect; read: DMA0 channel 3/7 transfer complete interrupt disabled

1 (1): write: enable DMA0 channel 3/7 transfer complete interrupt; read: DMA0 channel 3/7 transfer complete interrupt enabled
SETENA4

CTI0 or DMA0 error interrupt set-enable bit

0 (0): write: no effect; read: CTI0 or DMA0 error interrupt disabled

1 (1): write: enable CTI0 or DMA0 error interrupt; read: CTI0 or DMA0 error interrupt enabled
SETENA5

FLEXIO0 interrupt set-enable bit

0 (0): write: no effect; read: FLEXIO0 interrupt disabled

1 (1): write: enable FLEXIO0 interrupt; read: FLEXIO0 interrupt enabled
SETENA6

Timer/PWM module 0 interrupt set-enable bit

0 (0): write: no effect; read: Timer/PWM module 0 interrupt disabled

1 (1): write: enable Timer/PWM module 0 interrupt; read: Timer/PWM module 0 interrupt enabled
SETENA7

Timer/PWM module 1 interrupt set-enable bit

0 (0): write: no effect; read: Timer/PWM module 1 interrupt disabled

1 (1): write: enable Timer/PWM module 1 interrupt; read: Timer/PWM module 1 interrupt enabled
SETENA8

Timer/PWM module 2 interrupt set-enable bit

0 (0): write: no effect; read: Timer/PWM module 2 interrupt disabled

1 (1): write: enable Timer/PWM module 2 interrupt; read: Timer/PWM module 2 interrupt enabled
SETENA9

Low Power Periodic Interrupt Timer interrupt set-enable bit

0 (0): write: no effect; read: Low Power Periodic Interrupt Timer interrupt disabled

1 (1): write: enable Low Power Periodic Interrupt Timer interrupt; read: Low Power Periodic Interrupt Timer interrupt enabled
SETENA10

Serial Peripheral Interface 0 interrupt set-enable bit

0 (0): write: no effect; read: Serial Peripheral Interface 0 interrupt disabled

1 (1): write: enable Serial Peripheral Interface 0 interrupt; read: Serial Peripheral Interface 0 interrupt enabled
SETENA11

Serial Peripheral Interface 1 interrupt set-enable bit

0 (0): write: no effect; read: Serial Peripheral Interface 1 interrupt disabled

1 (1): write: enable Serial Peripheral Interface 1 interrupt; read: Serial Peripheral Interface 1 interrupt enabled
SETENA12

LPUART0 status and error interrupt set-enable bit

0 (0): write: no effect; read: LPUART0 status and error interrupt disabled

1 (1): write: enable LPUART0 status and error interrupt; read: LPUART0 status and error interrupt enabled
SETENA13

LPUART1 status and error interrupt set-enable bit

0 (0): write: no effect; read: LPUART1 status and error interrupt disabled

1 (1): write: enable LPUART1 status and error interrupt; read: LPUART1 status and error interrupt enabled
SETENA14

Inter-Integrated Circuit 0 interrupt set-enable bit

0 (0): write: no effect; read: Inter-Integrated Circuit 0 interrupt disabled

1 (1): write: enable Inter-Integrated Circuit 0 interrupt; read: Inter-Integrated Circuit 0 interrupt enabled
SETENA15

Inter-Integrated Circuit 0 interrupt set-enable bit

0 (0): write: no effect; read: Inter-Integrated Circuit 0 interrupt disabled

1 (1): write: enable Inter-Integrated Circuit 0 interrupt; read: Inter-Integrated Circuit 0 interrupt enabled
SETENA16

Reserved iv 32 interrupt set-enable bit

0 (0): write: no effect; read: Reserved iv 32 interrupt disabled

1 (1): write: enable Reserved iv 32 interrupt; read: Reserved iv 32 interrupt enabled
SETENA17

PORTA Pin detect interrupt set-enable bit

0 (0): write: no effect; read: PORTA Pin detect interrupt disabled

1 (1): write: enable PORTA Pin detect interrupt; read: PORTA Pin detect interrupt enabled
SETENA18

PORTB Pin detect interrupt set-enable bit

0 (0): write: no effect; read: PORTB Pin detect interrupt disabled

1 (1): write: enable PORTB Pin detect interrupt; read: PORTB Pin detect interrupt enabled
SETENA19

PORTC Pin detect interrupt set-enable bit

0 (0): write: no effect; read: PORTC Pin detect interrupt disabled

1 (1): write: enable PORTC Pin detect interrupt; read: PORTC Pin detect interrupt enabled
SETENA20

PORTD Pin detect interrupt set-enable bit

0 (0): write: no effect; read: PORTD Pin detect interrupt disabled

1 (1): write: enable PORTD Pin detect interrupt; read: PORTD Pin detect interrupt enabled
SETENA21

PORTE Pin detect interrupt set-enable bit

0 (0): write: no effect; read: PORTE Pin detect interrupt disabled

1 (1): write: enable PORTE Pin detect interrupt; read: PORTE Pin detect interrupt enabled
SETENA22

Low Leakage Wakeup 0 interrupt set-enable bit

0 (0): write: no effect; read: Low Leakage Wakeup 0 interrupt disabled

1 (1): write: enable Low Leakage Wakeup 0 interrupt; read: Low Leakage Wakeup 0 interrupt enabled
SETENA23

Integrated interchip sound 0 interrupt set-enable bit

0 (0): write: no effect; read: Integrated interchip sound 0 interrupt disabled

1 (1): write: enable Integrated interchip sound 0 interrupt; read: Integrated interchip sound 0 interrupt enabled
SETENA24

Universal Serial Bus interrupt set-enable bit

0 (0): write: no effect; read: Universal Serial Bus interrupt disabled

1 (1): write: enable Universal Serial Bus interrupt; read: Universal Serial Bus interrupt enabled
SETENA25

Analog-to-Digital Converter 0 interrupt set-enable bit

0 (0): write: no effect; read: Analog-to-Digital Converter 0 interrupt disabled

1 (1): write: enable Analog-to-Digital Converter 0 interrupt; read: Analog-to-Digital Converter 0 interrupt enabled
SETENA26

Low-Power Timer interrupt set-enable bit

0 (0): write: no effect; read: Low-Power Timer interrupt disabled

1 (1): write: enable Low-Power Timer interrupt; read: Low-Power Timer interrupt enabled
SETENA27

RTC seconds interrupt set-enable bit

0 (0): write: no effect; read: RTC seconds interrupt disabled

1 (1): write: enable RTC seconds interrupt; read: RTC seconds interrupt enabled
SETENA28

INTMUX0 channel 0 interrupt interrupt set-enable bit

0 (0): write: no effect; read: INTMUX0 channel 0 interrupt interrupt disabled

1 (1): write: enable INTMUX0 channel 0 interrupt interrupt; read: INTMUX0 channel 0 interrupt interrupt enabled
SETENA29

INTMUX0 channel 1 interrupt interrupt set-enable bit

0 (0): write: no effect; read: INTMUX0 channel 1 interrupt interrupt disabled

1 (1): write: enable INTMUX0 channel 1 interrupt interrupt; read: INTMUX0 channel 1 interrupt interrupt enabled
SETENA30

INTMUX0 channel 2 interrupt interrupt set-enable bit

0 (0): write: no effect; read: INTMUX0 channel 2 interrupt interrupt disabled

1 (1): write: enable INTMUX0 channel 2 interrupt interrupt; read: INTMUX0 channel 2 interrupt interrupt enabled
SETENA31

INTMUX0 channel 3 interrupt interrupt set-enable bit

0 (0): write: no effect; read: INTMUX0 channel 3 interrupt interrupt disabled

1 (1): write: enable INTMUX0 channel 3 interrupt interrupt; read: INTMUX0 channel 3 interrupt interrupt enabled

Links

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Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data